@GTV reviews the Cosmic Fantasy 1-2 Switch collection by Edia, provides examples of the poor English editing/localization work. It's much worse for CF1. Rated "D" for disappointment, finding that TurboGrafx CF2 is better & while CF1's the real draw, Edia screwed it up...
Main Menu

Can it be done? save RAM inside TE?

Started by wilykat, 08/07/2015, 04:48 AM

Previous topic - Next topic

0 Members and 1 Guest are viewing this topic.

wilykat

Turbobooster, Turbobooster Plus, Tennokoe, and Backup Booster plus CD systems all have save RAM for in game saves. (there's also Save-kun and M128 but those are not usable with most games).

Express and GT do not and they do not have the expansion connector for one.

I have been looking at Tennokoe (cheapest) and it seems like I can cut the board to minimum including the custom NEC chip plus SRAM chip, add a super cap to the SRAM's + rail with a diode in line so the cap can be charged when TE is powered on, and keep SRAM from getting erased:
IMG

I've documented the pinouts from the EXT connector to the chip and SRAM and I'd need to clean up my notes, type it in text file, and double-check it all. Then figure out which CPU pins to tap.

Some of the components on one side of the bank is used for battery watchdog and can be removed in favor of a super cap and a diode. (was 4 transistors plus a dozen caps and resistors cheaper than one super cap back then?)

The only issue is about 30 wires from CPU to the save board.  Since Tennokoe didn't use some of the expansion pinouts (CD detect, video bus, etc) it cuts down some work from the full 69 pins but that's still a lot of work to do.  Also would I still have room to install it in a TE?  The wide ribbon cable from the mainboard to the cart board would be in the way.

wilykat

IMG

light red shaded area on NEC to EXT connector are no connection.  The middle EXT pinout are just for reference, and the third EXT pinout are those used by SRAM, those are shared with NEC chip.

Most of the connection are between custom NEC chip and the ext connector, with a few address lines shared with SRAM chip.  And a few connection (data and rest of address) are strictly between NEC chip and SRAM chip.  SRAM doesn't have its own connection to the EXT bus.

Preliminary detail, I still need to double check that I didn't miss any connection or get any wrong but this seems about right.  And it happens that all of the required pins can be tapped right off the cart connector so I could just tap onto the ribbon connector rather than directly off the CPU.  I'd suggest getting 5v and ground elsewhere, closer to the internal 5v regulator.

The only limiting factor is if I can get the board small enough to fit in the space between controller board and battery compartment with the cap mod to the SRAM for data retention.  And that my idea for a diode and cap is enough to hold data on SRAM for more than a few days without draining the batteries.

Even with the new LCD on my express, the password screen is still a pain in the ass to deal with so battery backed ram for some games would be wonderful.

thesteve

some of the neopce cards have save ram

Fidde_se

Where would the implementation of the save/ram menu be inserted, it should be loaded at startup like the CD menu, it might interfere with hu-cards, maybe a switch "to choose" a card with those instructions.
GW/GB/GBP/GBL/GBC/GBA/GBASP/GBASP2/GBM/DS/DSL/DSiXL/3DS/PM/VB/FC/NES/SNES/N64/GC/Wii/PS/PSONE/PS2/PS2S/
SMS/SMS2/GG/NOM/MD/MD2/MD3/MD1CD/SS/DC/XB/XB360/NGP/NGPC/NGPC2/WS/WSC/CSW/PCEGT/PCE/PCECG1/PCECG2/
PCECD/TG16TE/NGAGE/GIZ/GP32/GP2XF1/GP2XF2/GP2XWIZ/GP2XCAN/DA320/ST520/ST1040/LNX/LNX2/JAG/PORT/CD32/A500/
C64/CDi/VMU/POCKSTN/PSP/PSPCFW/FDS/VSM

wilykat

Quote from: Fidde_se on 08/08/2015, 06:43 AMWhere would the implementation of the save/ram menu be inserted, it should be loaded at startup like the CD menu, it might interfere with hu-cards, maybe a switch "to choose" a card with those instructions.
There is no built in menu, the access to memory is dependent on the software such as Neutopia and CD system cards. Hucard that don't have save support simply ignores the save RAM.

To be clear, the save hardware I am using is Tennokoe 2 which is basically the same as Backup Booster or Turbobooster Plus, without external AV ports.  I am not doing anything with Tennokoe Bank card which does use Hucard slot and can't be used at the same time as Hucard games.

wilykat

#5
^^ bump ^^

coming fresh off that BRAM hack I did on my Duo, I have set my eyes on this.  Instead of cutting up the old Tennokoe2 board I'd try to make a new PCB, transplant the propriety HuC6201 chip and add in 2k SRAM or FRAM.  The smallest FRAM seems to be 8kx8 so I would have to ground extra address to lock them in 2k bank, maybe a cut away jumper trace if I decide to convert it to multi-paged mode?

Right now I need to figure out the correct pin spacing on HuCard slot so I can make easy solder-on connection to the PCB, and to find an odd 64 pin QFP solder pad in the library, the ones I found were all 16 pins by 16 pins square, none that is 10 pins long by 13 pins wide.

EDIT: I found 2 errors in the chart above.  B10 goes to NEC 28 not 26, and C16 goes to SRAM 2 not 21.  Also I omitted the VCC and GND:

NEC 25 is VCC
SRAM 24 is battery backed VCC (can use cap and a diode or with FRAM, direct to VCC)
NEC 26, 58, and SRAM 12 are GND

thesteve

ok here is a thought
how is save addressed?
if its a hard address then this is simple, but if its mapped not so much

wilykat

Addressed the same way as TurboBooster Plus and Tennokoe.  Some Hucard games can access the save this way, and this is what I am aiming for.  Trying to read or type in password for Neutopia 2 on a tiny screen is too much hassle.  :D

One could use System card or BRAM viewer (via TED) to access the save RAM to check for files and reformat them.

wilykat

Prelim schematic:
IMG
The pin number on connectors are for Hucard slot connectors. Since all of the required lines are at Hucard slot, it should be fairly easy to tap into the connector.

The 8 data lines correspond to TG-16 pinout and from the HuC6201 chip, 8 lines needs to be flipped (15 and 23, 16 and 22, 17 and 21, and 19 and 20) to work on PCEngine, LT, and GT.

Also LED is optional, I left it in as a status indicator but won't be present on final form.  Also I am going with FRAM so I don't need to deal with caps. FRAM doesn't come smaller than 32kx8 so there's 4 jumper pads to tie them to ground and lock them in specific 2k block for now. The jumper will allow me to add the switch mod I made in other thread for the board to be used in TG-16 and PCE/CGFx as there's room in those consoles.  TE and GT does not have much room.

FWIW this is not useful in Duo for obvious reason.

thesteve

ok i suspect im looking at an address range decoder
can we get a programmer to give the address range, and if its shared or not
determine the proper addressing scheme and we should be able to set up a GAL or 2 as the interface circuit, so there is no need to destroy an official save device

blueraven

This thread is awesome. Thank you guys for doing this.

OldMan

#11
IF I remember right (and I may not...)

Quoteok i suspect im looking at an address range decoder
You need to watch $1803 in the I/O area (bank $7f?). One of the bits 'unlocks' the BRAM.
I think it then appears at $8000. I don't -think- you need to map it in.

Best bet is to ask bonknuts or elmer. They seem to really know the hardware from a programming pov.

EDIT:
Just checked the bios code. It maps the I/O page to $8000-$9fff,  before unlocking BRAM. Not sure how that works, but it then checks for the format string at $8000...
Unlock bit is 7 ($80).

wilykat

That is what I figured.  That HuC6201 is used as a watchdog that monitors specific address and data and connects 2k SRAM to the game when the condition is right.  Sort of like a bankswitching chip.

I think CPLD is the minimum needed because there's 20 addresses, 8 data, optional LED output, battery checker, and reset plus some address, /ce, /oe, and 8 data, to connect.  The schematic I did above should help figure out the design.

thesteve

well consider this
the data lines can go directly to the RAM as CE can put the RAM into tri-state
if the RAM is directly addressed then the addresses also can go directly to RAM
that leaves a supporting chip requirement being to decode CE as RD WR should be from system bus directly

OldMan

Quotethe data lines can go directly to the RAM as CE can put the RAM into tri-state
Wouldn't you need all the address lines to catch the unlock address?

thesteve

well yes, but that could be a flash chip in itself
simply having the unlock address programmed into a rom
say a 29f800 with all its data low except the unlock address 1 bit high and the access range a different bit high
that would cover the address decoding, then you would just need an 8 input 1 output gal for the unlock data
add another input or a nor gate and it becomes latching

wilykat

Someone's going to have to get what's left of NEC to cough up the original datasheet for HuC2601 or any useful details. Otherwise someone will have to dump the chip somehow.

I don't know how it's supposed to work and I have no idea if SRAM can have the data connected directly to the bus or not.  It is possible that HuC6201 has to be the one with data access.

A shitload of data sniffer and feeding address one at a time until you see something and see what it does and how it works.  If the data into HuC6201 and data out to SRAM are the same, then that can save a few pins on replacement CPLD. If they are different for some reason, then no.

OldMan

Quotewell yes, but that could be a flash chip in itself
simply having the unlock address programmed into a rom
Didn't think of that. So you could use a chip to detect the $7f (io page) part of the address, and use that output to turn the chip on so the programmed data would appear on the data lines?
Maybe. The BRAM unlock is different register on a read, though, iirc.

I think you could do it, just don't think it would be as simple as it appears.
Just to satisy my curiosity, could you put an 8 bit A-B switch in a small programmable device? If so, it might make things easier...(Switch between BRAM and regular memory based via the switch)

thesteve

dont know about that, but it woundnt be needed
you just enable the chip you want to access

wilykat

#19
In the meanwhile after making a custom pad for HuC6201, it seems no one made a 13x19 SOIC pad that I can use.  I have made a quick test board to see if all could fit:

IMG

Red area are the controller PCB supports (rough approximate, a 12" long (30cm) caliper that's over 30 years old is not made for measuring small space), there is room for the whole thing but I may need to hack and split that 38 pin connector (solder on ribbon cable) into 2x 19 and offset it so the cable wouldn't get pinched somewhere between the new board and the cart connector end.

I am still playing with part positioning and traces to see what can work

thesteve

just a note
on the TE/GT the motherboard is the same, only the cart slot board is wired different

wilykat

I updated the board with a few support that I omitted from the original measurement and despite my best effort I can get all but one wire done. I may have to use jumper.  I had to remove the 4 jumper pads and the LED to reduce the number of incomplete connection, I could use jumper and clip anyway for checking LED.

https://www.dropbox.com/s/ub86szklfjpw1mk/Psx.zip?dl=0

If you're experienced with Eagle and want to try playing with the component placement or wiring.

wilykat

I think I got it. I changed the 3 caps to be SMD and I was able to make it complete.  Shrunk the PCB by removing empty spaces and I'll get it sent off to OSHPark to see if the board works and fits as I hope.